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按键去抖动

已有 143 次阅读2019-11-12 10:40 |个人分类:FPGA_Verilog|系统分类:硬件设计

module debouncer
    (
    input           key_in,
    input           clk_100m,

    output  reg     key_out,
    output  reg     syn_1ms
    );

reg     [16:0]      cnt_1ms;
always @ (posedge clk_100m)
begin
    if (cnt_1ms >= 17'd99_999)
        cnt_1ms <= 17'd0;
    else
        cnt_1ms <= cnt_1ms + 17'd1;
end

always @ (posedge clk_100m)
begin
    if (cnt_1ms >= 17'd99_999)
        syn_1ms <= 1'b1;
    else
        syn_1ms <= 1'b0;
end

reg     [4:0]       cnt_20ms;
reg                 sample_en;
always @ (posedge clk_100m)
begin
    if (syn_1ms == 1'b1)
    begin
        if (cnt_20ms >= 5'd19)
            cnt_20ms <= 5'd0;
        else
            cnt_20ms <= cnt_20ms + 5'd1;
    end
    else ;
end

always @ (posedge clk_100m)
begin
    if (cnt_20ms == 5'd19 && syn_1ms == 1'b1)
        sample_en <= 1'b1;
    else
        sample_en <= 1'b0;
end

reg                 key_in_dly1;
reg                 key_in_dly2;
reg                 key_in_dly3;

always @ (posedge clk_100m)
begin
    if (sample_en == 1'b1)
    begin
        key_in_dly1 <= key_in;
        key_in_dly2 <= key_in_dly1;
        key_in_dly3 <= key_in_dly2;
    end
    else ;
end

wire                key_in_act;
wire                key_in_deact;
assign key_in_act = key_in_dly1 || key_in_dly2 || key_in_dly3;
assign key_in_deact = key_in_dly1 && key_in_dly2 && key_in_dly3;

always @ (posedge clk_100m)
begin
    if (key_in_act == 1'b0)
        key_out <= 1'b0;
    else if (key_in_deact == 1'b1)
        key_out <= 1'b1;
    else ;
end

endmodule

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